wafer-level

基本解釋

One should cover the resistance with metal layer, to avoid the damaged during the wafer level testing.
用金屬覆蓋電阻,避免wafer級測試時的損傷。
Structure designing and key processing technologies for wafer level package(WLP) were studied.
對圓片級封裝(WLP)的結(jié)構(gòu)設(shè)計和關(guān)鍵工藝技術(shù)進行了研究;
Electrostatic bonding is an important encapsulating means for the materials at the chip or wafer level.
靜電鍵合是片狀材料封接的一種重要手段，討論了玻璃在電場作用下的鍵合過程。
Research of gold bump for wafer level package
用于圓片級封裝的金凸點研制
Ultrathin Wafer Level Chip Size Package Technology
超薄型圓片級芯片尺寸封裝技術(shù)